Computer work stations generally include one or more central processor units (CPUs), memory units, storage units, user input devices, and display devices. When the work station is turned on, a disk operating system program such as Windows or UNIX is automatically loaded into memory from a storage unit (e.g. a hard drive), and then the program is executed by the CPU. A prompt or prompt of icons appears on the display unit such as a cathode ray tube (CRT) or liquid crystal display (LCD) screen. Most current systems use a graphical interface in which a mouse is used to move a cursor onto a menu or icon to select a command and then a button on the mouse is clicked to execute the commands. Other programs such as word processors, spread sheets, and internet browsers may be executed by inserting removable media such as a floppy disk or CD-ROM into a disk drive to form a storage unit and then using an operating system command to load the program into memory and initiate execution of the program. Text is entered using a keyboard once the program is operating.
The programs include instructions and data such as numbers and characters (text). During execution the CPU transmits addresses of program instructions and data onto a plurality of parallel signal wires known as an address bus. The address bus has enough signal lines to transmit all the bits of the address simultaneously (typically 32 lines). The memory unit responds by transmitting the respective instructions or data onto a plurality of parallel signal wires known as a data bus. The data bus has enough signal lines to transmit all the bits of a memory cell (typically 32 or 64 bits) simultaneously along the parallel lines. The CPU stores the fetched data into registers (very fast memory) in the CPU and executes the fetched instructions. The instructions command the CPU to perform some activity on the numbers and characters such as add or multiply the numbers, or such as compare two characters or copy the data to some memory address. Some instructions called jumps compare data and then control the address from which subsequent instructions will be fetched depending on the comparison. This allows the CPU to execute a small section of the program in a loop--that is, the CPU executes the same series of instructions over and over again until some task is complete.
For example, while executing a graphics based word processing program, a user presses a key to replace a character on the display and then the CPU executes a series of instructions to copy a picture of the character from a font portion of memory onto a display portion of memory. The display is made up of hundreds of thousands of small dots called pixels. Each character on the display covers an area that may include 100 pixels. The display of each pixel may be controlled by several numbers. Ten instructions may be required to copy each number from the font portion to the display portion of memory. Those ten instructions would be executed over and over again in a loop for each number of each pixel until the character appeared on the display.
Leading edge work stations currently operate at a clock frequency of 200 million times per second (200 MHZ) and the operating frequency of the newest leading edge work stations have been about doubling every two years. Current design and development activities are planned for producing machines that operate as fast as 500 MHZ. Instructions are executed in a pipeline that usually completes one instruction every clock cycle so that a 500 MHZ machine would execute up to 500 million instructions per second or one instruction every 2 nano seconds (ns).
In order to achieve the highest speeds possible the communications between computer units are usually synchronized using a clock signal. That is a clock signal is generated and distributed to each unit of the computer and communications are timed according to the clock. For example, the CPU transmits a request for data at the beginning of a clock cycle and expects a response at by the end of the following clock cycle. Such clock signals are typically provided by crystal oscillators. A capacitor is formed by depositing metal on two opposite surfaces of a piezoelectric crystal. The crystal capacitor is connected in parallel to an RLC circuit with about the same frequency as the natural frequency of the crystal. The crystal stabilizes the frequency of the RLC circuit to produce a signal that closely approximates a square wave and does not drift in frequency. The output signal of the crystal circuit (clock signal) is distributed to each unit of the computer and used for synchronizing data transmission.
Data such as addresses, numbers, characters, control signals are transmitted using binary codes either electrically over copper lines or optically through glass filaments. The signal is either on or off. For electrical signals on or one is usually a positive potential such as 5 volts and off or zero is usually a low potential such as 0 volts. The signals consist of a multitude of ones and zeros. Characters are coded as binary numbers and numbers and the coded characters are transmitted as binary (base 2) numbers.
The memory of a work station operating at 500 MHZ must be capable of transmitting an instruction onto the data bus every 2 ns or the CPU would have to wait for the next instruction. Two types of devices are typically used for work station memory. Dynamic random access memory (DRAM) is relatively cheap but accessing data requires up to 60 ns. Static random access memory (SRAM) is much more expensive but much faster and is expected to operate at access speeds of 2 ns (required to feed instructions to a CPU operating at 500 MHZ). In typical work stations, most of the memory is DRAM and a much smaller portion (5 to 20%) is SRAM. The SRAM is used as a cache to store a copy of frequently used instructions and data. When instructions and data are accessed they are copied from the DRAM to the SRAM. Most programs constantly reuse small portions of the program such as loops. Depending on the program, 90% of fetches may be made from a cache that includes only 10% of the system memory.
In order to achieve higher speeds, the design of SRAM memory has to be rigorously optimized for high-speed access. Due to tolerances in the manufacturing process including both dimensional and material tolerances, many of the products produced for high speed can not pass operational testing for such speeds. Because SRAMs operate internally at a high speed the product that fails operational testing at high speed can not easily be used at a lower speed. Furthermore, operating temperatures and external voltage levels affect the internal speed of the memory so that timing may not be within tolerances during operation and computer failure may result.
U.S. Pat. No. 5,546,354 to Partovi describes an SRAM in which the internal timing can be adjusted by applying tuning signals to some of the pins so that fast SRAM that has failed testing can be used as a slower SRAM in a computer that provides such tuning signals.
U.S. Pat. No. 5,546,355 to Raatz describes a SRAM with a self-timed write pulse so that minor fluctuations in the external clock signal do not cause incorrect data to be written into the memory array. Delay elements adjust the write pulse to compensate for temperature, power supply, and process variations.
U.S. Pat. Nos. 5,566,325 to Bruce, II; 5,333,293 to Bonella; and 5,276,858 to Oak disclose adaptive approaches to timing problems using DRAM memory.
All the above citations are hereby incorporated in whole by reference.